1. Field of the Invention
The present invention relates to computer system architecture. More particularly, the present invention relates to microprocessor bus protocols for cache memories to improve computer system throughput.
2. Art Background
A common technique for improving computer system throughput is to employ a cache memory. A cache memory is a limited size fast memory, usually made up of static RAMs (SRAMs) which store blocks of data, known as lines, that reflect selected external memory locations. A cache memory is smaller than the external memory it reflects, which means that the cache memory is typically not fully addressable, and must store a tag field for each data line. A tag field identifies the external memory address corresponding to a particular data line.
When the processor issues a read request and an address corresponding to a desired data line, the cache memory is checked by comparing the address to tag fields maintained by a cache controller. If the desired data line is stored in the cache, a hit occurs, and the desired data line is available to the processor. If the desired data line is not stored in the cache, a miss occurs, and the desired data line must be fetched from slower external memory.
In prior cache memory systems, a read transaction typically requires three steps: the processor transmitting an address to the cache, the cache controller checking the tags, and the processor reading the data line from the cache if a hit occurs. Thereafter, the processor transmits a next address to the cache and the sequence repeated. In fact, this three step sequence repeats for each data line read from the cache.
Similarly, prior cache systems typically require a three step write transaction: the processor transmitting an address and corresponding data line to the cache, the cache controller checking the tags, and the cache controller storing the data line in the cache. The processor then transmits a next address and data line to the cache and the sequence repeats.
In prior cache memory systems, achieving higher throughput rates required decreasing the latency of bus signals. However, as higher clock frequencies are used, latency limits are reached because of the inherent physical characteristics of bus signal lines. For example, increasing frequencies cause problems with signal reflections on the bus signal lines.
As will be described, the present high performance microprocessor bus protocol improves system throughput by performing read burst and write burst bus transactions to a cache, and by interleaving bus transactions during external fetch cycles for missed cache lines. Bus performance is improved by achieving high throughput at high bus frequencies, despite physical constraints on overall bus latency.